The present disclosure described herein relates to a semiconductor memory system, and more particularly, relates to a termination resistance calibration method of a semiconductor memory device including a termination resistance.
A memory system may include a controller and a semiconductor memory device connected to a transmission line. A data signal transmitted along the transmission line may be reflected at an end of the transmission line. The reflected data signal may become noise and may affect an original data signal, thus, quality of the data signal may be lowered. A termination resistance may be connected to the end of the transmission line to prevent the data signal from being reflected. The termination resistance is a component used to reduce reflection of the data signal and to prevent lowering of quality of the data signal, by matching between an internal impedance and an external impedance of a semiconductor memory device. The termination resistance is typically used for a DRAM having a high operation speed. Recently, to prevent signal interference between DRAMs, an ODT (On Die Termination) technique is used for connecting the termination resistance to the interior of the DRAM.
Since the DRAM may have an operation speed higher than 1000 MHz under, for example, DDR3 SDRAM (Double Data Rate 3 Synchronous DRAM) standards, higher quality and stability of the data signal may be required. If impedance is not matched due to a variation in a value of the termination resistance according to a variation in a fabrication process, a power supply voltage, and an operation temperature, it may be difficult to transmit a data signal at high speed, and data is often distorted. The DDR3 SDRAM may use ZQ calibration logic to secure high signal quality and stability. The internal impedance and the external impedance of the semiconductor memory device may be matched by calibrating the termination resistance according to a calibration code generated by the ZQ calibration logic. Examples of ZQ calibration are described in U.S. Pat. No. 7,859,296 to Kim et al., and U.S. Pat. No. 8,111,085 to Ibaraki et al., both of which are incorporated by reference herein in their entirety.
However, time for calibrating the termination resistance is limited. According to typical ZQ calibration logic, calibration intervals for each of pull-up and pull-down resistances are partially overlapped due to time limitation, thus, reliability of calibration may be lowered. If the number of bits of the calibration code is reduced to overcome the time limitation, accuracy of encoding is decreased, thus, a characteristic of a data output driver is negatively influenced. In addition, if a value of the termination resistance is largely changed according to a PVT (Process, Voltage, and Temperature) variation, an accurate impedance matching may be impossible.
According to a typical technique, impedance matching is performed by using fuses to manually adjusting the value of the termination resistance. However, this calibration method may be limited in that calibration time for impedance matching is increased and automatic calibration may be impossible.